There is a current interest in CMOS active pixel imagers for use as low cost imaging devices. FIG. 1 shows a conventional CMOS active pixel sensor imager array circuit 100 including a pixel array 110 and associated circuitry. Circuit 100 includes an array 110 of pixels 150 and a row decoding/controlling circuit 130 and a column address/decoding/readout circuit 120 which provide timing and control signals to enable reading out of signals stored in the pixels 150 in a manner commonly known. The array 110 has columns 149 and rows 147 of pixels 150. Exemplary arrays 110 have dimensions of M times N pixels 150, with the size of the array 110 depending on a particular application. The imager 100 is read out a row 147 at a time using a column parallel readout architecture. The row circuit 130 selects a particular row 147 of pixels 150 in the array 110 by controlling the operation of row addressing and row drivers (not shown) within the row circuit 130. Charge integration signals stored in the selected row of pixels 150 are provided on the column lines 170 to a column circuit 120, in a manner described below, and sampled and stored in column buffer circuits 151. The pair of signals corresponding to the read out reset signal and integrated charge signal (e.g., Vrst, Vsig) are provided by the column buffer circuits 151 to a differential amplifier circuit 154. The differential amplifier circuit 154 provides the differential output of the pixel signals (e.g., Vrst, Vsig) to the analog-to-digital (ADC) circuit 156. The ADC circuit 156 provides a digital value representing the signal of the pixel 150 output to associated circuitry 199. Associated circuitry 199 is representative of the many circuits that receive the input from the ADC circuit 156 and perform operations on the input. For example, associated circuitry 199, may store, transfer to a bus/memory, and perform linear/non-linear operations on the signal input.
A pixel 150 of the CMOS active pixel sensor imager array 100 is shown in greater detail in FIG. 2. Pixel 150 can have one or more active transistors within the pixel unit cell, can be made compatible with CMOS technologies, and promises higher readout rates compared to passive pixel sensors. The FIG. 2 pixel 150 is a 3T APS, where the 3T is commonly used in the art to designate use of three transistors to operate the pixel. A 3T pixel has a photodiode 162, a reset transistor 184, a source follower transistor 186, and a row select transistor 188. It should be understood that while FIG. 2 shows the circuitry for operation of a single pixel 150, in practical use there will be an M times N array of identical pixels 150 arranged in rows and columns with the pixels 150 of the array accessed using row and column select circuitry, as described above.
The photodiode 162 converts incident photons to electrons which collect at node A. A source follower transistor 186 has its gate connected to node A and amplifies the signal appearing at node A. When a particular row-containing cell 150 is selected by a row selection transistor 188, the signal amplified by transistor 186 is passed on a column line 170 to the readout circuitry. The photodiode 162 accumulates a photo-generated charge in a doped region of the substrate. It should be understood that the pixel 150 might include a photogate or other photoconversion device, in lieu of a photodiode, for producing photo-generated charge.
A reset voltage source Vrst, typically Vaa, on line 195 is selectively coupled through reset transistor 184 to node A. The row select control line 160 is coupled to all of the pixels 150 of the same row of the array. Voltage source Vaa is coupled to a source following transistor 186 and its output is selectively coupled to a column line 170 through row select transistor 188. Although not shown in FIG. 1, column line 170 is coupled to all of the pixels of the same column of the array and typically has a current sink at its lower end. The gate of row select transistor 188 is coupled to row select control line 160.
The gate of reset transistor 184 is coupled to reset control circuit 180 through reset control line 191. Reset control circuit 180 serves to control the reset operation in which Vrst is coupled to node A. Reset control circuit 180 may provide a plurality of control signals to the reset transistor 184, e.g., the reset control circuit 180 provides a full and an intermediate reset signal to reset transistor 184. Reset control circuit 180 is mutually coupled to the reset transistor 184 of each pixel 150 in the row 147. Each row 147 of pixels 150 has an associated reset control circuit 180.
As known in the art, a value is read from pixel 150 in a two-step process. During a charge integration period, the photodiode 162 converts photons to electrons which collect at the node A. The charges at node A are amplified by source follower transistor 186 and selectively passed to column line 170 by row access transistor 188. During a reset period, node A is reset by turning on reset transistor 184 and the reset voltage is applied to node A and read out to column line 170 by the source follower transistor 186 through the activated row select transistor 188. As a result, the two different values—the reset voltage Vrst and the image signal voltage Vsig—are readout from the pixel and sent by the column line 170 to the readout circuitry where each is sampled and held for further processing as known in the art.
FIG. 3 more clearly shows the column buffer circuit 151 of FIG. 1 that is capable of sampling and holding and then providing two sampled values, e.g., Vsig and Vrst values, for subsequent use by a down stream circuit (FIG. 1). As seen in FIG. 3 the column line 170 is switchably coupled through SH_R switch 310 to the first side of capacitor 318. The second side of capacitor 318 is switchably coupled through switch 326 to a downstream circuit. The column line 170 is also switchably coupled through SH_S switch 310 to the first side of capacitor 320. The second side of capacitor 320 is switchably coupled through switch 328 to a downstream circuit. The first side of capacitor 318 is switchably coupled through switch 313 to the first side of capacitor 320. A clamp voltage Vcl is switchably coupled through switch 315 to the second side of capacitor 318. A clamp voltage Vcl is also switchably coupled through switch 317 to the second side of capacitor 320.
The conventional CMOS imager array 100 (FIG. 1) has a limited dynamic range and is prone to over-saturation from receiving a very high light intensity. As is known in the art, the dynamic range of a pixel array can be increased by implementation of an extended dynamic range (XDR) technique, where a modified reset signal is applied to the gate of the reset transistor. The modified reset signal, referred to as an intermediate reset value, has a different, typically smaller, amplitude than the “full reset” signal asserted at the start of each integration period. The intermediate reset value will affect only those cells on which a strong light signal is incident. Only if a photocurrent has reduced the voltage across a cell's photodiode to below a certain level at the time the intermediate reset value is asserted, then the voltage across the photodiode will be pulled up to Vdac=Vxdr−Vth, where Vxdr is the voltage, i.e., of the intermediate voltage, on the reset line 191 (FIG. 2) and Vth is the threshold voltage of the reset transistor (e.g., reset transistor 184 of FIG. 2). In accordance with the XDR technique, during each integration period, the intermediate reset value is applied to the gate of each of the reset transistors in the row.
FIG. 4 depicts a Vadc output of an upstream pixel from an imager system when the XDR technique is applied. By applying an intermediate reset value during the integration period, the response curve of the image sensor is converted from a linear curve to a piecewise linear curve, as illustrated in FIG. 4.
The vertical axis of FIG. 4 represents digital data output from circuit 156 (FIG. 1), i.e., an ADC amplifier 156, as a result of a read of an upstream pixel 150 of the imager 100 (FIG. 1). The Vzero 411 axis represents a zero (“0”) Vadc output. The Vadc_break 413 axis represents a Vadc output of the kneepoint (e.g., the break point). The Vadc_max 417 axis represents a maximum Vadc output of a pixel 150, e.g., the saturation point. The horizontal axis in FIG. 4 represents incident light intensity on the cell during the integration period. The Lzero 401 axis represents a zero (“0”) light intensity output. The Lbreak 403 axis represents a light intensity output of the kneepoint. The Lno_XDR 405 axis represents a maximum light intensity output of a pixel 150 if an XDR technique is not applied, e.g., the saturation point of the pixel without an extended dynamic range. The LXDR 407 axis represents a maximum light intensity output of a pixel 150 if an XDR technique is applied, e.g., the saturation point of the pixel with an extended dynamic range.
Curve 410 represents the response curve of pixel 150 (FIG. 1), indicating the range of detectable incident light intensity (from Lzero 401 to Lno_XDR 405) corresponding to the full range of the output of ADC amplifier 156 (FIG. 1), from Vzero 411 to Vadc_max 417, when no intermediate reset signal is asserted during the integration period. Curve 420 of FIG. 4 represents the response curve of the pixel 150, indicating the extended range of detectable incident light intensity (from Lzero 401 to LXDR 407, where intensity LXDR 407 is greater than Lno_XDR) corresponding to the full range of the output of ADC amplifier 156, when an intermediate reset signal is asserted during the integration period. The break point 430 represents the change in the response of pixel 150 to light intensity after an intermediate pulse signal is provided, i.e., after the XDR technique is applied. At breakpoint 430, the response curve changes from the non-extended range light intensity curve 410 to the extended range light intensity curve 420.
FIG. 4 illustrates how the XDR technique extends the dynamic range of the image sensor, namely by increasing the maximum detectable light intensity from Lno_XDR 405 to LXDR 407. The coordinates of the breakpoint (403, 413) depend on the photodiode voltage immediately after an XDR reset (Vdac=Vxdr−Vth) and the time at which the XDR reset is performed during the integration period. It is possible to perform two or more intermediate resets in a single integration period, which results in a piecewise linear sensor response curve having N+1 linear sections, and N breakpoints (one breakpoint for each of N intermediate resets), and can (in some cases) increase the dynamic range beyond that achievable with only one intermediate reset per integration period.
When implementing the XDR technique, the voltage supplied to the reset line 191 (FIG. 2) can be generated using a DAC (digital-to-analog converter). The imager 100 (FIG. 1) can be programmed with a desired intermediate voltage level and the time at which each XDR reset is performed.
FIG. 5 illustrates how the XDR technique affects the digital output from an ADC circuit 156 (FIG. 1) of an upstream pixel cell 150 over time. The vertical axis of FIG. 5 represents voltage data output from circuit 156 (FIG. 1), i.e., an ADC amplifier 156, as a result of a read of an upstream pixel 150 of the circuit 100 (FIG. 1).
The Vzero 511 axis represents a zero (“0”) Vadc output. The Vadc_break 515 axis represents a Vadc output of the kneepoint. The Vadc_max 517 axis represents a maximum Vadc output of a pixel 150, e.g., the saturation point.
The horizontal axis in FIG. 5 represents time. The Tzero 501 axis represents time zero (“0”). The time Trst 503 axis represents the time of the kneepoint, e.g., the time that the intermediate reset voltage is applied. The time Tint 507 axis represents the total integration time of a pixel 150, regardless whether a XDR technique is applied, e.g., the saturation point of the pixel with an extended dynamic range.
Curve 550 represents the response curve of pixel 150 (FIG. 1) when the XDR mode is disabled and the intermediate reset is not applied. The slope of curve 550 (i.e., dV/dt) is proportional to the photocurrent of pixel 150 and the intensity of light incident on pixel 150. As drawn, curve 550 corresponds to the maximum light intensity that can be sensed by pixel 150 without saturation when XDR is off, Imax_noxdr. Any curve with a steeper slope, like curve 510, will cause the output of pixel 150 to saturate at Vadc_max 517.
Curves 510 and 520 represent the response curve of pixel 150 when the XDR mode is enabled. Any pixel 150 receiving more light than that represented by curve 540 will be affected by the intermediate reset. While a full reset would cause integration to restart from Vzero, the intermediate reset restarts integration from Vadc_intrst 513 and continues for a duration of (Tint-Trst). During this second period of integration the maximum light intensity that will not cause pixel saturation is represented by the slope of curve 520, Imax_xdr.
Curve 510 represents the response curve of pixel 150 (FIG. 1) indicating the range of time (from Tzero 501 to Trst 503) corresponding to the full range of the output of the ADC amplifier 156 (from Vzero 511 to Tint 517), when no intermediate reset signal is asserted during the integration period. Curve 520 of FIG. 5 represents the response curve of pixel 150, indicating the extended range of time, Tint (from Trst 503 to Tint 507, where Tint 507 is greater than Trst 503) corresponding to the full range of output of the ADC amplifier 156 when an intermediate reset signal is asserted during the integration period at the breakpoint time period Trst 503.
Point 530 shows that, upon application of the intermediate reset signal, the response of pixel 150 to photon integration changes. At time period 503, the response curve changes from the non-extended range voltage output curve 510 to the extended range voltage output curve 520. The Vadc_instr 513 represents the change in Vrst that is provided, i.e., the full reset value offset by the intermediate reset value.
FIG. 5 illustrates how the XDR technique extends the dynamic range of the image sensor, namely by increasing the maximum amount of exposure for the pixel 150 without causing the signal from the pixel 150 being over saturated.
A pixel array with an XDR system can be programmed to provide a desired kneepoint by specifying the desired Trst (i.e., intermediate reset time) and intermediate reset voltage Vrst. However, within sensor circuitry are inherent sources of variation affecting absolute signal magnitudes. Although a XDR system is designed to provide intermediate and full reset voltages, process variation can affect the provided voltage, resulting in actual intermediate and full reset voltages, which are different from the desired intermediate and full reset voltages. Therefore, the desired knee point may differ from the actual knee point.
The knee point corresponds to the time when the intermediate reset voltage is applied and the voltage output from the pixel at the break point, i.e., Vadc_break. The knee point can be determined by first determining the difference between the full reset voltage and the intermediate reset, i.e., ΔVrst. Since values of Trst and Tint are pre-determined, Vadc_break can be calculated once ΔVrst is determined, where:Vadc_break=(Tint/Trst)*ΔVrst  (1).
However, it is unknown how to determine the actual difference between the full reset voltage and the intermediate reset, i.e., ΔVrst. Consequently, it is not been known how to determine the actual knee point of the response curve. Thus, it would be desirable to be able to determine the actual knee point of the response curve.